In recent years, sampling circuits for sampling analog signals have been utilized in various fields, and they are modified into various systems that are suitable for the respective fields. In particular, in image displays such as liquid crystal displays, sampling circuits for sampling video signals are adopted in data-signal-line driving circuits, which will be described below.
For example, in a liquid crystal display of the active-matrix driving system, multiple scanning signal lines and multiple data signal lines are installed in an intersecting manner, and a pixel is disposed in each area enclosed by the adjacent scanning signal lines and the adjacent data signal lines. Thus, multiple pixels are disposed in the form of matrix.
Each pixel is provided with a switching device consisting of an FET (Field Effect Transistor) of the MOS type, and a pixel capacity. The switching device is conducted by a signal given to the scanning signal line so that it receives data (video signal) given to the data signal line, and supplies the data to the pixel capacity.
The data signal lines receive video signals that have been sampled by a data-signal-line driving circuit, and the scanning signal lines are successively selected by the scanning-signal-line driving circuit. Through the selections of the scanning signal lines, the video signals, which are given to the respective data signal lines, are written to the pixels, and held therein.
This writing process of data to the data signal lines is carried out using the point-sequential driving method or the line-sequential driving method.
In the point-sequential driving method, the inputted video signals are written to the data signal lines by opening and closing the sampling switch installed in the sampling circuit in synchronism with pulses that are released from a plurality of outputs of a shift register. In this method, supposing that the number of data lines in the horizontal direction is n, the time that allows the video signals to be written to the data signal lines is only as short as a 1/n of an effective horizontal scanning period (approximately 80% of the horizontal scanning period). For this reason, when the time constant (product of capacity and resistance) of the data signal lines becomes greater upon adopting large screens to meet the current demands, it is difficult to maintain a sufficient writing process, thereby causing adverse effects on the quality of displayed images.
In particular, this problem is aggravated when the sampling switch is constituted of transistors with low driving performance, such as multi-crystal thin-film transistors which will be described later. Therefore, in conventional arrangements, the channel width of the transistors constituting the sampling switch is set to be greater in order to maintain a sufficient writing process.
In the line-sequential driving method, the sampling switch is opened and closed in synchronism with pulses that are released from a plurality of outputs of a shift register, in the same manner as the point-sequential driving method. Moreover, in the line-sequential driving method, the inputted video signals are temporarily stored in sampling capacities, and then released to the data signal lines through a buffer amplifier during the next horizontal scanning period.
In general, since the sampling capacities are smaller than the capacities of the data signal lines, the line-sequential driving method makes it possible to shorten the time during which the video signals are inputted from the video signal line and are written to the data signal lines. Further, the writing process to the data signal lines, which requires a greater load, is carried out during the horizontal scanning period; this allows a sufficient writing process to the data signal lines. As described above, the line-sequential driving method has less problems than the point-sequential driving method.
However, the disadvantage of the line-sequential driving method is that the electric charge held in the sampling capacity decreases due to leakage current in the sampling switch as time elapses and it also decreases due to capacity divisions upon transferring data to the buffer amplifier. In order to suppress these adverse effects, it is proposed that the sampling capacity be increased; however, this might cause an insufficient writing process in the same manner as caused in the point-sequential driving method. Therefore, in this case, also, it is necessary to increase the channel width of the transistors constituting the sampling switch in order to maintain a sufficient writing process.
Here, for example, as shown in FIG. 47, the above-mentioned sampling circuit is provided with a group of inverters 202 consisting of a plurality of stages of series connected inverters 201 and a sampling switch 203 consisting of only n-channel transistors. In this sampling circuit, when the video signal from the video signal line VL is written to the data signal line SL, an output signal from the shift register 204, which forms a timing signal, is amplified by the group of the inverters 202, and is inputted to the gate electrode of the sampling switch 203.
As shown in FIG. 48, the inverter 201 has a construction wherein an n-channel transistor 201a and a p-channel transistor 201b are connected in series with each other.
During the writing process, the sampling switch 203 requires a high-level signal V.sub.H that is sufficient to write the video signal on the high-voltage side in its conducted state, while it requires a low-level signal V.sub.L that allows the holding of the video signal on the low-voltage side in its cutoff state. Therefore, during the writing process, it is necessary to substantially increase the amplitude of the signal to be given to the gate electrode of the sampling switch 203.
More specifically, supposing that the amplitude of the video signal is V.sub.sig, the threshold voltage of the sampling switch 203 is V.sub.tn, and the on-margin and off-margin of the sampling switch 203 are V.sub.on and V.sub.off respectively, signals V.sub.H and V.sub.L are indicated as follows: EQU V.sub.H =V.sub.sig +V.sub.tn +V.sub.on (1) EQU V.sub.L =-V.sub.sig +V.sub.tn -V.sub.off (2)
Here, the on-margin represents a voltage to be added to the threshold voltage of the sampling switch 203 in order to provide a sufficient writing process, and the off-margin represents a voltage to be subtracted from the threshold voltage of the sampling switch 203 in order to substantially reduce the leakage current. For example, typical values for the respective voltages are: V.sub.sig =5(V), V.sub.tn =2(V), V.sub.on =4(V), and V.sub.off =5(V). In accordance with equations (1) and (2), signals V.sub.H and V.sub.L are represented as follows based on these values. EQU V.sub.H =5+2+4=11(V) EQU V.sub.L =-5+2-5=-8(V)
Therefore, it is necessary to provide a source voltage of 19V that is the voltage difference between V.sub.H and V.sub.L. Accordingly, the elements need to have a withstand voltage of up to 19V.
Moreover, FIGS. 49 and 50 show other sampling circuits, each of which is provided with a group of inverters 205(206) consisting of a plurality of steps of inverters 201, and a sampling switch 207. The group of inverters 205(206) is branched into two signal paths from the inverter 201 at the second stage from the shift register 204, and a plurality of steps of inverters 201 are installed in each signal path.
The sampling switch 207 has a CMOS construction wherein n-channel and p-channel type transistors 207a and 207b are connected in parallel with each other. In this sampling switch 207, the video signal on the low-voltage side is written by the n-channel transistor 207a and the video signal on the high-voltage side is written by the p-channel transistor 207b.
During the writing process, the output signal of the shift register 204 is inputted to the n-channel transistor 207a and the p-channel transistor 207b through the inverters 201 and some logical circuits (not shown) which are installed as occasion demands. The inverters 201 are installed so as to drive the sampling switch 207 having a great channel width (having a great input load) by the use of the output of the shift register 204 having a small driving power as well as to adjust the phase (polarity) of signals. The later the stage of the inverter 201, the greater the channel width of the transistor that is used in the inverter 201. The logical circuits are installed so as to control the sampling timing so that only the minimum video signals required are sampled. It is necessary for the input signals to the n-channel transistor 207a and the p-channel transistor 207b to have phases that are reversed to each other. For this reason, the difference between the numbers of the inverters 201 in the signal path to the n-channel transistor 207a and the inverters 201 in the signal path to the p-channel transistor 207b is set to an odd number (normally set to one).
In general, the above-mentioned sampling circuit is driven by a single power supply (in this case, V.sub.cc and V.sub.ss); therefore, the voltage levels of the input signals to the gate electrodes of the transistors 207a and 207b are kept the same. Then, the voltage level is given so that each transistor 207a (207b) is brought to a complete cutoff state.
The above-mentioned voltage level has to be set large enough to allow the video signal to be written to the data signal line SL upon conduction of the transistors 207a and 207b. The level is also set to a size that allows the written video signal to be held until the next writing process upon cutoff of the transistors 207a and 207b. Here, the leakage current of the transistors 207a and 207b is at a level that is not negligible even if it is below the threshold voltage; therefore, it is necessary to provide a certain amount of reversed bias voltage (negative bias voltage in the n-channel transistor 207a) in order to obtain a sufficient holding characteristic.
Normally, when such a bias voltage as to lead the complete cutoff is applied to one of the transistors (n or p) having one polarity, the other transistor having the other polarity is sufficiently conducted to allow a sufficient writing process of the video signal; therefore, it is not necessary to take into consideration voltages under normal conditions. In other words, it is only necessary to provide voltages that make the transistors cut off completely.
More specifically, supposing that the amplitude of the video signal is V.sub.sig, the threshold voltage of the n-channel transistor 207a is V.sub.tn, the threshold voltage of the p-channel transistor 207b is V.sub.tp and the off-margin of the sampling switch 207 is V.sub.off, signals V.sub.H and V.sub.L are indicated as follows: EQU V.sub.H =V.sub.sig +V.sub.tp +V.sub.off (3)
V.sub.L =-V.sub.sig +V.sub.tn -V.sub.off (4)
For example, typical values for the respective voltages are: V.sub.sig =5(V), V.sub.tn =2(V), V.sub.tp =-2(V), and V.sub.off =5(V). In accordance with equations (3) and (4), signals V.sub.H and V.sub.L are represented as follows based on these values. EQU V.sub.H =5-2+5=8(V) EQU V.sub.L =-5+2-5=-8(V)
Therefore, it is necessary to provide a source voltage of 16V that is the voltage difference between V.sub.H and V.sub.L. Accordingly, the elements need to have a withstand voltage of up to 16V.
In conventional active-matrix-type liquid crystal displays, an amorphous silicon thin-film formed on a transparent substrate is used as a substrate material for a switching device. Further, the liquid crystal display is provided with a scanning-signal-line driving circuit and a data-signal-line driving circuit as externally attached driving-use ICs.
In recent years, however, in order to meet demands for improvement in the driving performance of switching devices as well as for reduction in assembling costs of the above-mentioned driving-use ICs and other demands that are raised to satisfy the current trend for large screens, a technology has been suggested and already reported wherein a pixel array consisting of pixels disposed in the form of matrix and both of the driving circuits are monolithically formed on a polycrystal silicon thin film. Moreover, in order to achieve large screens and low costs, it has been proposed that switching devices and other devices are formed on a polycrystal silicon thin film on a glass substrate under processing temperatures not more than the distortion point of glass (about 600.degree. C.).
However, in such a construction where sampling circuits are formed on a polycrystal silicon thin film, various problems have been raised because of inferior characteristics of the devices.
One problem is that the withstand voltage of those devices is low (that is, the devices deteriorate greatly when stress is applied), compared to that of the transistors formed on a mono-crystal silicon substrate. In particular, this problem is aggravated in the case of multi-crystal silicon thin-film transistors formed on a glass substrate. In fact, although it depends on the manufacturing process, the construction of the devices, the channel widths and other factors, the withstand voltage between the source and drain in these transistors is around 15V.
Moreover, compared to mono-crystal silicon transistors, the carrier mobility of multi-crystal silicon transistors is rather small, that is, about one-tenth thereof; this results in a far inferior driving performance. For this reason, signals with a higher level are required upon conduction, in order to provide a sufficient writing operation for video signals on the high-potential side. In addition, it is necessary to use devices of large size in order to obtain a driving power as high as that of the mono-crystal silicon transistors.
Furthermore, another problem is that since multi-crystal silicon thin-film transistors have a greater sub-threshold factor, a conventional off-margin causes a large leakage current. For this reason, signals with a lower level are required upon cutoff, in order to suppress the leakage current so that video signals on the low-potential side can be held.
Therefore, in the multi-crystal silicon thin-film transistors, it is necessary to provide signals having an amplitude greater than that in the mono-crystal silicon transistors, from the aspects the carrier mobility and the sub-threshold factor. However, in the case of constituting the group of inverters 202 and the sampling switch 203 by using multi-crystal silicon thin-film transistors, it is impossible to apply high voltages to the devices because of their low withstand voltage. As a result, problems, such as insufficient writing operation for video signals or fluctuations in video signals due to leakage current, might occur and the quality of displayed images might be diminished.
Here, the application of the sampling switch 207 makes the amplitude of required signals become smaller to a certain extent. However, there are still some cases in which the amplitude of the signals exceeds the withstand voltage of the multi-crystal silicon thin-film transistors, and as with the application of the sampling switch 203, the same problems, such as insufficient writing operation for video signals or fluctuations in video signals due to leakage current, might occur and the quality of displayed images might be diminished.
As described above, when a driving circuit, constituted by groups of transistors that are inferior in their characteristics to mono-crystal silicon transistors, is adopted, one of the conventional problems is that it is not possible to obtain a sufficient writing operation.
Moreover, in the sampling circuits having the constructions as shown in FIGS. 49 and 50, the numbers of the inverters 201 are different between the signal path to the n-channel transistor 207a and the signal path to the p-channel transistor 207b; this causes a slight difference in delay time upon transferring signals, and thus causes offsets in the timing of conduction and cutoff in the transistors 207a and 207b. As a result, fluctuations in signal levels tend to occur upon writing video signals, thereby causing an inaccurate writing operation. The following description will discuss the reasons for this problem in more detail.
When the transistors 207a and 207b are cut off, noise is generated between the source electrode and gate electrode of each transistor due to its parasitic capacity. This noise is caused by a potential change in the gate electrode after the cutoff of the transistor; therefore, the noise generated at the n-channel transistor 207a has negative polarity and the noise generated at the p-channel transistor 207b has positive polarity. The magnitude of the noise is proportional to the channel width of the transistor.
If the timings of the cutoffs coincide with each other between the n-channel transistor 207a and the p-channel transistor 207b, and if the magnitudes of the noises are the same between them, the noises are virtually cancelled. However, if there is an offset between the timings of the cutoffs, noise remains due to the transistor having the delayed timing of the cutoff. For example, in the sampling circuit shown in FIG. 50, the signal path to the p-channel transistor 207b has more inverters 201 than the signal path to the n-channel transistor 207a by one stage; therefore, it has a longer path by one stage, and this causes a delay in the timing of the cutoff. Consequently, the potential of the data signal line SL is shifted in the positive direction.
When such a sampling circuit is applied to a data-signal-line driving circuit, potential fluctuation occurs in video signals, thereby causing adverse effects on the liquid crystal displaying operation. In particular, in the case of multi-gradation displaying operation, it is difficult to obtain desired gradations. Further, in the case where transistors with greater channel widths are used to meet the demands for large screens and high resolution as described earlier, the adverse effects due to potential fluctuation are further aggravated. In addition, in the case of using devices having a small driving power, such as multi-crystal silicon thin-film transistors, it is necessary to widen the channel widths of the transistors, and the adverse effects due to potential fluctuation are further aggravated.
Here, as shown in FIG. 51, another method has been proposed (see SID 92 DIGEST pp.55-58) wherein a latch circuit consisting of two inverters 208 and 209 connected in parallel with each other in the reversed direction is inserted between two signal paths forming the input stages to inverters 201 that are disposed right before the transistors 207a and 207b, and this method aims to make the timings of the cutoffs coincide with each other between the n-channel transistor 207a and the p-channel transistor 207b.
In this method, however, it is necessary to increase the driving power for the inverters 208 and 209 constituting the latch circuit to a certain extent, in order to make the timings of signals in the two paths coincident with each other. In this case, there is a high possibility that the signal change becomes slow temporarily because of the input signals having different polarities and that a through current is caused temporarily since the intermediate potential has been maintained.
In the meantime, in the image displays of the active-matrix type as described earlier, a signal amplifier is installed at the output stage in order to amplify the signals in the data-signal-line driving circuit of the line-sequential type and other circuits. For use as such an amplifier, amplifiers having linear characteristics which allow an output that is proportional to an input are preferably used. Normally, operational amplifiers are used for this purpose, but cascode amplifiers, which require fewer devices, are sometimes used. In addition, the above-mentioned signal amplifier is also used in various apparatuses other than image displays, since it has characteristics which allow an output that is proportional to an input.
One example of such a cascade amplifier is described on page 324 in "Electronic Circuits for Transistors and ICs (II) 2nd. Edition" published by McGraw-Hill Book Company on Jul. 10, 1982. This cascode amplifier, which is constituted of two bipolar transistors of the same type connected in series with each other, features that although the dc levels are different between input and output, no attenuation occurs in the ac component.
FIG. 52 shows one example of a signal amplifier wherein cascode amplifiers consisting of FETs are used.
The signal amplifier is provided with two cascode amplifiers that are connected in series with each other. The cascode amplifier at the former stage is constituted of p-channel transistors 211 and 212 connected in series with each other that are disposed between the source terminal (voltage V.sub.CC) on the high-potential side and the source terminal (voltage V.sub.SS) on the low-potential side. Further, the cascode amplifier at the latter stage is constituted of n-channel transistors 213 and 214 connected in series with each other that are disposed between the above-mentioned source terminals. Predetermined bias voltages V.sub.BP and V.sub.BN are applied to the respective gate electrodes of the transistors 212 and 214 so that they function as constant current sources. The input signal is applied to the gate electrode of the transistor 211, and the output signal is drawn from the junction between the transistors 213 and 214.
With this arrangement where the two cascade amplifiers are installed in series with each other, the above-mentioned amplifier prevents the input level from being affected by the fluctuation in the output level.
However, the problem of the above-mentioned amplifier is that: upon receipt of an input signal with its level changing in an increasing fashion, an output responding to the level changes at high speeds is obtained; however, upon receipt of an input signal with its level changing in a decreasing fashion, it is not possible to obtain an input signal responding to the level changes at high speeds.
For this reason, even if the above-mentioned signal amplifier is applied to image displays of the active-matrix type, it is highly possible that the video signals are not written to the data signal line within a predetermined period of time. In particular, when it is applied to image displays with multi-gradation displaying function, the quality of the displayed images tends to be diminished.
Here, if the driving performance of the transistor 214 is increased, that is, if the stationary current in the transistor 214 is increased, it is possible to obtain an output responding to the level changes at high speeds, even upon receipt of decreases in the level of the input signal. However, increasing the driving performance of the transistor 214 causes an increase in power consumption.
In particular, in the case of transistors formed on a multi-crystal silicon thin film disposed on an insulating substrate, the carrier mobility is low, the threshold voltage is high, and the withstand voltage is low in comparison with transistors formed on a mono-crystal silicon substrate as described earlier; therefore, it is difficult to increase the driving performance of the transistor 214 beyond a certain limit.
Consequently, even if it is aimed to make high-quality image displays of the active-matrix type by monolithically forming pixel arrays and driving circuits on a multi-crystal silicon thin film disposed on an insulating substrate in order to meet the demands for large screens and inexpensive apparatuses, it is difficult to achieve this purpose as long as the conventional signal amplifiers are used.
In some conventional liquid crystal displays of the active-matrix driving type, switching devices, such as amorphous thin-film transistors, are provided on a light-transmitting type insulating substrate such as a glass substrate. In these liquid crystal displays, a display-use-electrode substrate, which has a construction where wiring, such as data signal lines and scanning signal lines, is formed together with switching devices, is used. The liquid crystal displays of this type have been widely used, because high-quality images are provided, because they have less limitation to the area on the light-transmitting type insulating substrate to be utilized as a display-use-electrode substrate, and because they are well suited for either type of liquid crystal displays of reflection-type and transmission-type.
In the above-mentioned liquid crystal displays, the driving circuits for supplying data signals and scanning signals to pixel portions having switching devices, that is, the data-signal-line driving circuit and the scanning-signal-line driving circuit, have to be connected to the display-use-electrode substrate. The following two methods and other methods are used as the connecting method: the film carrier method wherein a connecting film consisting of a polyimide-resin thin-film base or other bases whereon a number of copper-thin-film lines are formed is used; and the COG (Chip on Glass) method wherein driving circuits are directly packaged on the display-use-electrode substrate.
In recent years, the driver monolithic technique, which improves the packaging efficiency of circuit devices by integrally forming the driving circuits and switching devices, has been developed, as described earlier. However, as long as amorphous silicon thin-film transistors, which are currently being used, are adopted as the switching devices, it is difficult to fully realize the driver monolithic technique because of the deficiency in driving performance. Therefore, the driver monolithic technique wherein multi-crystal silicon thin-film transistors capable of improving the driving performance are adopted is currently being developed. These multi-crystal silicon thin-film transistors are formed by using multi-crystal silicon thin films as the semiconductor layers constituting the transistors.
As described above, it is essential to use the multi-crystal silicon thin films in order to realize the driver monolithic technique. However, the problems of the thin-film transistors are: only poor withstand voltage is available between the source and drain; a great difference exists between the threshold voltages of the NMOS transistor and the PMOS transistor; and the values of the threshold voltages themselves are great. Because of these problems in the thin-film transistors, signal amplifiers (buffer amplifiers), which are used in the driving circuits in a liquid crystal display, particularly, those used in the data-signal-line driving circuit as the output circuit at the last stage, have a problem that their linear-operation region is narrowed.
For example, a signal amplifier, shown in FIG. 53, is provided with two stages of source-follower-type linear circuits that function as the output circuit of the above-mentioned data-signal-line driving circuit. This signal amplifier is constituted of a linear circuit 221 of the NMOS type placed at the former stage and a linear circuit 222 of the PMOS type placed at the latter stage.
The linear circuit 221 is constituted of series connected n-channel transistors 223 and 224 that are placed between the source terminal (voltage V.sub.dd) on the high-potential side and the source terminal (voltage V.sub.ss) on the low-potential side. An input signal (input voltage) V.sub.in is inputted to the gate electrode of the transistor 223, and a bias voltage V.sub.BN is applied to the gate electrode of the n-channel transistor 224. Further, an output voltage V.sub.o to the linear circuit 222 is outputted from the junction of the transistors 223 and 224.
The linear circuit 222 is, on the other hand, constituted of series connected p-channel transistors 225 and 226 that are placed between the source terminal (voltage V.sub.dd) on the high-potential side and the source terminal (voltage V.sub.ss ') on the low-potential side. A bias voltage V.sub.BP is applied to the gate electrode of the p-channel transistor 225, and the output voltage V.sub.o is inputted to the gate electrode of the p-channel transistor 226. Further, an output voltage V.sub.out is outputted from the junction of the transistors 225 and 226.
Here, it is assumed that the n-channel transistors 223 and 224 and the p-channel transistors 225 and 226 have the same device characteristics respectively. Moreover, the bias voltage V.sub.BN is set to such a value that the n-channel transistor 224 operates within its saturated area. V.sub.bn is a potential difference between the gate and source when the bias voltage V.sub.BN is applied thereto. Similarly, the bias voltage V.sub.BP is set to such a value that the transistor 225 operates within its saturated area. V.sub.bp is a potential difference between the gate and source when the bias voltage V.sub.BP is applied thereto.
Supposing that the threshold voltage of the n-channel transistor 224 is V.sub.thn and the margin voltage for allowing the transistor 224 to operate within its saturated area with a certain amount of current is .alpha., the following equations hold with respect to the transistor 224: EQU V.sub.bn =V.sub.thn +.alpha. EQU V.sub.BN -V.sub.ss =V.sub.thn +.alpha. (5)
Further, supposing that the threshold voltage of the transistor 225 is V.sub.thp and the margin voltage for allowing the transistor 225 to operate within its saturated area with a certain amount of current is a in the same manner as the transistor 224, the following equations hold with respect to the transistor 225: EQU V.sub.bp =V.sub.thp -.alpha. EQU V.sub.BP-V.sub.dd =V.sub.thp -.alpha. (6)
Normally, the margin voltage .alpha. is set to 1 to 2 V, and the margin voltage .alpha. of the same magnitude is used both in the NMOS transistor and the PMOS transistor.
Next, an explanation will be given on the operation of the signal amplifier.
In the linear circuit 221, the potential difference V.sub.bn is provided between the gate and source of the n-channel transistor 224 so that its operation is performed within its saturated area. In this case, a current I.sub.sd.sub..sup.2 flowing between the source and drain of the n-channel transistor 224 is represented by the following equation, since the operation takes place within the saturated area. EQU I.sub.sd.sub..sup.2 =(1/2).multidot.Cox.multidot..mu.(W/L).multidot.(V.sub.bn -V.sub.thn).sup.2
wherein
Cox: Capacity of gate insulating film PA1 W: Channel width of transistor PA1 .mu.: Carrier mobility PA1 L: Channel length of transistor.
The path of current Isd1 flowing through the n-channel transistor 223 is branched toward the following stage at the junction between the n-channel transistors 223 and 224, and this branched current path is connected to the gate electrode of the transistor 226, thereby remaining in a virtually open state electrically. Therefore, in this stationary state, I.sub.sd.sub..sup.1 is represented as I.sub.sd.sub..sup.1 =I.sub.sd.sub..sup.2 .
Since the potential difference between the gate and source, which allows the current I.sub.sd.sub..sup.2 to flow through the transistor 224, is V.sub.bn and the device characteristics of the n-channel transistors 223 and 224 are the same, the potential difference between the gate and source of the n-channel transistor 223 is also represented by V.sub.bn, and the output voltage V.sub.o of the first-stage circuit 1 is represented by: EQU V.sub.o =V.sub.in -V.sub.bn.
As for the linear circuit 222 at the following stage, since the potential difference V.sub.bp is given between the gate and source of the p-channel transistor 225 so that its operation takes place within the saturated area, the same operation as in the preceding stage is carried out except for the difference in polarity. Therefore, V.sub.out is represented as follows: EQU V.sub.out =V.sub.o -V.sub.bp.
Thus, V.sub.out satisfies the following relationship with respect to v.sub.in : EQU V.sub.out =V.sub.in -V.sub.bn -V.sub.bp (7)
Here, the ideal input-to-output characteristic in the signal amplifier is: EQU V.sub.out =V.sub.in.
Therefore, this signal amplifier has an offset of -(V.sub.bn +V.sub.bp).
FIG. 54 shows the input-to-output characteristics of the signal amplifier.
In FIG. 54, curve E indicates the input-to-output characteristic of the linear circuit 221, and curve F indicates the input-to-output characteristic of the linear circuit 222. The input voltage V.sub.in to the signal amplifier is indicated by line segment L.sub.1, and the output voltage V.sub.o is, on the other hand, indicated by line segment L.sub.2 that corresponds to a straight-line portion of curve E and that is given as an output range within the linear-operation region of the linear circuit 221.
Next, when the output voltage V.sub.o is indicated by line segment M.sub.1 as an input signal to the linear circuit 222, the output voltage V.sub.out is indicated by line segment M.sub.2 that corresponds to a straight-line portion of curve F and that is given as an output range within the linear-operation region of the signal amplifier. In this case, the output range (line segment M.sub.1) within the linear-operation region of the linear circuit 221 has a large portion that exceeds an input range (line segment M.sub.3) that corresponds to the linear-operation region of the linear circuit 222, and this exceeding portion is represented by the length of line segment N.
As explained above, the linear-operation region of the signal amplifier is narrowed. Further, the greater the absolute value of the threshold voltage, the greater the bias voltage V.sub.BN has to be set, and at the same time the smaller the bias voltage V.sub.BP has to be set. Moreover, the greater the difference between the absolute values of the threshold voltages of the NMOS transistor and the PMOS transistor, the longer the line segment N. Thus the linear-operation region of the signal amplifier is further narrowed.
Here, in order to expand the linear-operation region of the signal amplifier, it is proposed that the source voltage should be increased; however, this requires a higher withstand voltage in the transistors. As described earlier, it is generally known that multi-crystal silicon transistors, which are essential to the driver monolithic technique, are inferior to mono-crystal silicon transistors in their withstand voltage, and it is difficult to increase the withstand voltage.
Moreover, in order to obtain optimum buffer characteristics, it is proposed that the above-mentioned offset, -(V.sub.bn +V.sub.bp), should be eliminated. This is satisfied when the absolute values of the threshold voltages of the NMOS transistor and the PMOS transistor are equal to each other. However, in general, the absolute value of the threshold voltage of the PMOS transistor is greater than that of the NMOS transistor.
Here, the above-mentioned condition can be satisfied by setting the margin voltage .alpha. within the potential difference V.sub.bn between the gate and source of the NMOS transistor to a value greater than required. However, the greater the potential difference V.sub.bn,V.sub.bp between the gate and source of each transistor, the further the operation of the transistor is dislocated from the saturated area. This makes it impossible for the linear circuit to carry out a normal operation, thereby narrowing the linear-operation region that is required as the signal amplifier.
Therefore, the above-mentioned method cannot make an effective solution since the linear-operation region of the signal amplifier is extremely narrowed, although it satisfies V.sub.out =V.sub.in by eliminating an offset with respect to a certain input voltage.
As described above, in the source-follower type linear circuit, when each transistor is driven by the same power supply, the linear area of the input-to-output characteristics is narrowed due to the bias voltage that has been affected by offsets. Moreover, the linear-operation region of the linear circuit can be expanded by increasing the source voltage; however, this method is limited by the withstand voltage of the transistors. Furthermore, the conventional signal amplifier is susceptible to offsets in the case when there are different threshold voltages between the NMOS transistor and the PMOS transistor.